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synchronizing signal generator for video camera description the CXD1217M is a synchronizing signal generator for color video cameras. features compatible with the respective systems, ntsc, palm, pal and secam output is synchronized with the clock of 910f h or 908f h 25hz offset processing by pal system color framing by the respective systems, ntsc, palm and pal possible external synchronization by h reset, v reset and line alternate reset pins applications synchronizing signal generator for color video cameras structure silicon gate cmos ic absolute maximum ratings (ta = 25?) supply voltage v dd v ss ?0.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 4.5 to 5.5 v operating temperature topr ?0 to +75 ? ?1 e89626b16-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD1217M 28 pin sop (plastic)
?2 CXD1217M 2 3 4 5 6 7 8 12 14 16 17 19 20 21 22 24 25 26 27 28 v dd ovd ohd olalt oblk ofld osync obf/colb ofld1 test o2fh osc ext mode1 mode2 hcomout clout clin ofh v ss 9 10 4fscin 4fscout 1/4 1/9 1/101 f h clock elimination 1/7 1/81 1/2 2f h pal palm f h pal palm 1/4 sc reset pal palm fv/2 f h 1/625 1/525 pal 1/625, 1/525 fv/8 int-ntsc int- ntsc sc reset 1/4 1/454, 1/455 1/625, 1/525 2f h field 1 reset 1/2 output f.f. 1 vri vertical reset 23 hri horizontal reset line alternate reset 15 laltri decode f h note) pin 19 output is (a) a signal based on pin 26 in int mode at ntsc. (b) each signal is based on pin 10 in other modes. phase comparison composite signal control f.f. block diagram and pin configuration
3 CXD1217M pin description pin no. symbol i/o description vertical reset signal first field output burst flag/color blanking output composite sync output even and odd output composite blanking output line alternate output horizontal drive output 4fsc output 4fsc input vertical drive output gnd pin line alternate reset input test input 2f h output (double the frequency of pin 27) sub carrier output internal and external synchronizing modes switchover l: internal synchronization h: external synchronization system selecting input 1 system selecting input 2 horizontal reset input phase comparator output clock output clock input horizontal frequency output power supply pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 i o o o o o o o o i o i i o o i i i i o o i o vri ofld1 obf/colb osync ofld oblk olalt ohd 4fscout 4fscin nc ovd nc v ss laltri test o2fh nc osc ext mode1 mode2 hri hcomout clout clin ofh v dd
4 CXD1217M electrical characteristics dc characteristics (v dd = 5v 10%, v ss = 0v, topr = 20 to +75 c) item output voltage 1 output voltage 2 ? 1 output voltage 3 ? 2 input voltage input current ? 3 (pull-down pin) output leak current ? 1 power current supply feedback resistance ? 4 symbol conditions i oh = 2ma i ol = 4ma i oh = 4ma i ol = 4ma i oh = 4ma i ol = 8ma v ih = v dd at high impedance at output pin in no-load v dd = 5v min. v dd 0.5 v ss v dd 0.5 v ss v dd /2 0.7v dd 20 250k 50 30 8 v dd 0.4 v dd 0.4 v dd /2 0.3v dd 120 2.5m v v v v v v v v a na ma ? typ. max. unit item input pin output pin symbol c in c out conditions min. 9 11 pf pf typ. max. unit ? 1 hcomout pin ? 2 4fscout and clout pins ? 3 laltri, test, ext, mode1 and mode2 pins ? 4 4fscout, 4fscin, clout and clin pins i/o capacitance (v dd = v i = 0v, f m = 1mhz) v oh v ol v oh v ol v oh v ol v ih v il i ih i lz i dd r fb
5 CXD1217M description of operation (see block diagram.) the cxd1217 is applicable to four systems; namely, ntsc, pal, palm and secam. in order to realize them, the following relative equations of sub-carrier (4fscln) and clock (clin) are adopted . as it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the pal and palm. therefore matching of the clock frequency is carried out by providing pll. 1 . mode specified input the cxd1217 provides four inputs to specify the respective modes. ? ext input: set this pin to v dd side, and it becomes into external synchronizing mode. at this time, the counters in connection with the pll ioop as shown in the upper part of the block diagram become into stand still state. ? mode1 and mode2 inputs: these are inputs for the system selection. ? test input: an input to be used to measure ic. this input is normally kept opened. (because it is dropped internally to vss with mos resistance.) 2. reset operation the cxd1217 has three reset inputs ; namely, hri, vri, laltri, and it works to perform reset operation when it detects falling edge. these three inputs are so designed as to take in synchronization with the ic internal clock. therefore, it is a prerequisite that both systems should have clock frequencies that are matched as a reset operation to each other (gen iocked). h reset (hri input) when the hri input is continuous with h synchronization, resetting is activated with the initial falling edge, and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns) against the initial edge in the internal clock. that is, if the jitter of hri input is less than 140ns, it is absorbed. the minimum resetting pulse width is over 0.3s. the phase to be reset is the advanced point of 6.3 to 6.37s (= 90 to 91-bit 70ns) than the hri input as shown in the diagram below. reset 6.3 to 6.37 [s] hri input cxd1217 hd out output ntsc pal palm secam 4fsc = 910f h 4fsc = 1135f h + 2fv 4fsc = 909f h sub carrier clock 910f h 908f h 910f h 908f h mode1 0 0 1 1 mode2 0 1 0 1 system ntsc secam palm pal "0" v ss "1" v dd
6 CXD1217M v reset (vri input) when the vri is input as shown in figure below, osync can be reset at the same phase with the sync signal. aa aa reset state rising edge is to be behind from point falling edge permitted span 2 14 36 58 710 912 11 14 13 15 cxd1217 internal clock (2f h ) (see timing chart diagram) sync signal vri counter state v reset pulse after reset sync out 10 912 11 14 13 a a since the falling edge point in the diagram above (marked with ) is the boundary of reset, if the falling edge of the vri input traverses that point, it causes 1/2h deviation to the reset state. accordingly, if resetting is applied between two similar systems whose frequency are different, the v to which resetting is applied generates jitter of 1/2h. (when the resetting is applied continuously.) lalt reset (laltri input) phase relation between laltri pulse polarity and 2f h is the same as in the case of v resetting. resetting operation is basically required only in the external synchronizing mode (gen lock mode). however, even in the internal synchronizing mode, it sometimes requires h and v outputs whose phases are deviated against a certain output. in that case, it suffices to use two cxd1217s and conduct the operation as follows: cxd1217 ohd1 ovd1 cxd1217 ohd2 ovd2 vri2 vri2 clock shift reg. delay clock output input ? it suffices to set ic-1 and ic-2 into int mode. by varying the delay and shift reg. of the above diagram, any phases of ohd2 and ovd2 can be provided against the respective ohd1 and ovd1. 3. color framing in the case of internal synchronization in the individual ntsc, pal and palm systems, the phase relationships between sync of the 1st field and sub-carrier are kept stable regardless of the power supply being on or off. however, as the pal and palm systems are comprised of pll, the absolute values concerning the phase according to variation of the ambient temperature drifts.
7 CXD1217M timing chart output timing chart diagram cxd1217 ntsc, palm field 1 2 3 4 lalt out (palm) odd field 1 2 3 4 even odd even sync out bf/colb out (palm) field 1 2 3 4 12h 10h odd even bf/colb out (ntsc) odd even odd even 20h hd out blk out 9h vd out fld out 3h 3h odd even field 1 field 1 fld1 out (fv/4) (ntsc) fld1 out (fv/8) (palm) clin (ntsc) 4fscin (palm) sc out
8 CXD1217M cxd1217 pal, secam field 4 1 2 3 lalt out (pal) even field 4 1 2 3 odd even odd sync out bf/colb out (pal) field 4 1 2 3 10h 9h even odd bf/colb out (secam) even odd even odd 25h hd out blk out 7.5h ovd fld out 2.5h 2.5h even odd fld1 out (fv/8) (pal) fld1 out (fv/4) (secam) 4fscin (pal) sc out 9h 7h 8.5h 9h 7h
9 CXD1217M cxd1217 f h hd/cblk p139 n140 p315 n315 p96 n96 p169 n154 p66 n68 p22 n22 p32 n36 p78 n76 p34 n32 p66 n68 p420 n423 p388 n387 p140 n141 p90 n90 p169 n169 p145 n145 p454 n455 1 2 h p908 n910 h p: pal secam n: ntsc palm numerical figures show number of clocks f h hblk hsync bf eq vsync h. r. 2f h vd fld fld1 lalt (internal clock)
10 CXD1217M application circuit basic connection in individual systems basic connection in individual systems at internal synchronization mode (ext input = "0") is as follows. see waveform diagram for each output. 19 23 25 26 1 vri osc hri clout clin ovd ohd olalt oblk ofld osync obf/colb ofld1 o2fh ofh 9 10 4fscin 4fscout 1/4 v dd 14 28 v ss v dd 14.318mhz ( = 910f h ) 2 3 4 5 6 7 8 12 17 27 synthesizer olalt ntsc ? h/2 is output for lalt out even in ntsc mode. ? mode1, mode2, ext, test and laltri pins can be kept open. (if noise annoys, connect to vss by low impedance.) 21 22 24 mode1 mode2 hcomout clock elimination 1/7 1/81 f h s. c. reset 1/2 1/625 1/8 field 1/4 17.734mhz (4fsc) 9 10 4fsc in 4fsc out ovd ohd olalt oblk ofld osync obf/colb ofld1 o2fh ofh 2 3 4 5 6 7 8 12 17 27 23 1 vri hri 19 25 26 osc clout clin v dd 28 10k 10k v dd 14 v ss l. p. f vco synthesizer 14.187mhz ( = 908f h ) phase comparison f' h pal ? inverter of clin or clout pins are usable as vco. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
11 CXD1217M 21 24 mode1 hcomout phase comparison 1/9 1/101 f h 1/525 1/8 field 1 1/4 14.302mhz (4fsc) 9 10 4fsc in 4fsc out ovd ohd olalt oblk ofld osync obf/colb ofld1 o2fh ofh 2 3 4 5 6 7 8 12 17 27 23 1 vri hri 19 25 26 osc clout clin v dd 28 10k v dd 14 v ss l. p. f vco synthesizer 14.318mhz ( = 910f h ) s. c. reset f' h palm ? internal inverter is usable as vco. 10k v dd 23 25 26 1 vri hri clout clin ovd ohd olalt oblk ofld osync obf/colb ofld1 o2fh ofh v dd 14 28 v ss 14.187mhz ( = 908f h ) 2 3 4 5 6 7 8 12 17 27 synthesizer 22 mode2 9 10 4fscin secam ? colb is output to bf/colb out pin. ? s dr and s db are formed in pll using 908f h . application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
12 CXD1217M package outline unit: mm sony code eiaj code jedec code sop-28p-l04 package structure package material lead treatment lead material package mass 42/copper alloy solder plating epoxy resin 28pin sop (plastic) 18.8 0.1 + 0.4 15 28 0.45 0.1 1.27 9.3 2.3 0.15 + 0.4 0.1 0.05 + 0.2 0.5 0.2 0.2 0.05 + 0.1 7.6 0.1 + 0.3 10.3 0.4 14 m 0.24 sop028-p-0375 1 0.7g 0.15 sony corporation sct ass'y sony code eiaj code jedec code sop-28p-l04 package structure package material lead treatment lead material package mass 42/copper alloy solder plating epoxy resin 28pin sop (plastic) 18.8 0.1 + 0.4 15 28 0.45 0.1 1.27 9.3 2.3 0.15 + 0.4 0.1 0.05 + 0.2 0.5 0.2 0.2 0.05 + 0.1 7.6 0.1 + 0.3 10.3 0.4 14 m 0.24 sop028-p-0375 1 0.7g 0.15 lead specifications item lead material copper alloy lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.

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